The present invention relates to a mask data generation method for use in lithography performed in semiconductor fabrication process, and more particularly, it relates to a mask data generation method in which dimension correction is performed in generating, through optical simulation, mask data for a semiconductor integrated circuit device having a dual gate structure.
As is well known, for attaining desired performance of a semiconductor integrated circuit by reducing variation in transistor characteristics, it is very significant to highly precisely form a gate pattern of a transistor recently further refined.
Since the threshold voltage of each transistor is recently highly precisely controlled by reducing a driving voltage in a CMOS (complementary metal oxide semiconductor) device including an NMOS transistor and a PMOS transistor, what is called a dual gate structure is now mainly employed.
In the dual gate structure, a gate electrode made of polysilicon doped with an N-type impurity is used as a gate portion of the NMOS transistor and a gate electrode made of polysilicon doped with a P-type impurity is used as a gate portion of the PMOS transistor. In this case, the gate electrodes are formed by simultaneously forming an N-type gate and a P-type gate in one dryetch process using an etching mask patterned based on one mask data. At this point, even when masks with the same width are used, the finished dimension of the polysilicon electrode is frequently different between the N-type gate and the P-type gate. In the case where the finished dimensions are thus different depending upon the doped impurities in the dual gate structure, it is necessary to correct the dimension difference for securing desired transistor performance. Japanese Laid-Open Patent Publication No. 11-174658 (Literature 1) discloses a method for correcting this dimension difference.
On the other hand, a mask data generation method using optical simulation has been put to practical use as described in Japanese Laid-Open Patent Publication No. 01-019470 (Literature 2). This is because a dimension difference derived from a pattern shape difference owing to an optical proximity effect has become too large to ignore in accordance with recent refinement of a CMOS device.
It is, however, difficult to attain both pattern correction for correcting a dimension difference caused in dryetch between an N-type gate and a P-type gate different in the doped impurity and pattern correction for correcting a dimension difference caused by optical proximity effect upon a pattern layout.
This is for the following reason: The optical simulation performed for correcting a dimension difference is a method for correcting the optical proximity effect, and pattern dependency of the process dimension difference caused in the dryetch process between an N-type gate and a P-type gate cannot be incorporated into the correction for the optical proximity effect.
Furthermore, a correction quantity determined in Literature 1 is based on comparison between a designed dimension and a dimension obtained after dryetch (post-dryetch dimension), and therefore, a dimension difference derived from distance dependency of adjacent patterns is already included in a dimension difference caused by the optical proximity effect of lithography. Accordingly, the correction method disclosed in Literature 1 cannot be directly combined with mask data correction process using a pattern shape obtained by the general optical simulation.
In other words, although it is necessary to perform the optical simulation in accordance with the refinement of a device, the pattern correction for the difference in the conductivity type of impurities cannot be currently incorporated into the optical simulation performed for correcting the resist dimension difference caused in the exposure depending upon a pattern shape.
An object of the invention is overcoming the aforementioned conventional disadvantage, so that dimension correction for gate structures with different conductivity types can be incorporated into the optical simulation in generating mask data for a semiconductor integrated circuit device including the gate structures different in the conductivity types, namely, the so-called dual gate structure.